System and processor for implementing interruptible batches of instructions
US9477480B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jan 12, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, method, and computer program product are provided for scheduling interruptible hatches of instructions for execution by one or more functional units of a processor. The method includes the steps of receiving a batch of instructions that includes a plurality of instructions and dispatching at least one instruction from the batch of instructions to one or more functional units for execution. The method further includes the step of receiving an interrupt request that causes an interrupt routine to be dispatched to the one or more functional units prior to all instructions in the batch of instructions being dispatched to the one or more functional units. When the interrupt request is received, the method further includes the step of storing batch-level resources in a memory to resume execution of the batch of instructions once the interrupt routine has finished execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.