Method for reducing the overhead associated with a virtual machine exit when handling instructions related to descriptor tables
US9477505B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2012 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jan 24, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computerized method for efficient handling of a privileged instruction executed by a virtual machine (VM). The method comprises identifying when the privileged instruction causes a VM executed on a computing hardware to perform a VM exit; replacing a first virtual-to-physical address mapping to a second virtual-to-physical address mapping respective of a virtual pointer associated with the privileged instruction; and invalidating at least a cache entry in a cache memory allocated to the VM, thereby causing a new translation for the virtual pointer to the second virtual-to-physical address, wherein the second virtual-to-physical address provides a pointer to a physical address in a physical memory in the computing hardware allocated to the VM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.