Power leveling of a system under test
US9477566B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 12, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Dec 26, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2200/261
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Power leveling a system under test (SUT). An input signal is provided at an initial power level to the SUT. Multiple iterations are performed, each including measuring, over a specified measuring interval, power of a signal produced by the SUT in response to the input signal, and dynamically adjusting the power of the input signal in response. The measuring interval is increased over the iterations, thereby increasing accuracy of the measuring over the iterations while converging the signal to a specified power level. An initial power leveling operation may be performed for the SUT to establish a specified power level, after which the SUT is tested, during which multiple power leveling operations are performed, each including measuring power of a signal from the SUT over a specified measuring interval, and adjusting the input signal in response, thereby maintaining the specified power level during the testing while correcting for thermal droop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.