Distributed clock synchronization
US9478268B2 · kind B2 · utility
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10References
19Claims
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Key dates
| Filing date | Jun 12, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jun 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/07
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.