Methods and apparatus for multiple memory maps and multiple page caches in tiered memory
US9478274B1 · kind B1 · utility
9Cited by
5References
20Claims
0Family size
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Key dates
| Filing date | Jun 25, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Nov 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7201
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for computer systems having first and second memory tier having regions, physical memory having page caches that are shareable with multiple ones of the regions in the first memory tier and the regions in the second memory tier, and virtual memory having mmaps of ones of the regions in the first memory tier and ones of the regions in the second memory tier, wherein the mmaps are associated with multiple ones of the pages caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.