Semiconductor device and method of manufacturing the same

US9478547B2 · kind B2 · utility

Assignee

• RENESAS ELECTRONICS CORPORATION · JP

Inventors

• Hiroyuki Kunishima · Ibaraki, JP
• Masashige Moritoki · Yokohama, JP
• Toshiji Taiji · Yokohama, JP
• Youichi Yamamoto · Tokyo, JP

Key dates

• Filing date: Jun 3, 2015
• Grant date: Oct 25, 2016
• Expiry date: Jun 3, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/318

Abstract

Dishing of a plate of a capacitor is suppressed in a structure where the top of the plate is flush with a top of an interconnection. Double interlayer dielectric films are used to form a first recess and a second recess. The second recess has an opening on the bottom of the first recess. The first and second recesses are used to form a capacitor. The lower electrode of the capacitor has a bottom part along the bottom of the first recess. The lower electrode further includes a sidewall part having an upper end that projects along a side face of the second recess from the opening of the second recess up to a position between the opening of the second recess and a top of the upper interlayer dielectric film (the upper one of the double interlayer dielectric films).