Stacked chip image sensor with light-sensitive circuit elements on the bottom chip
US9478579B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2013 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Dec 16, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/809
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An example imaging sensor system includes a backside-illuminated CMOS imaging array formed in a first semiconductor layer of a first wafer. The CMOS imaging array includes an N number of pixels, where each pixel includes a photodiode region. The first wafer is bonded to a second wafer at a bonding interface between a first metal stack of the first wafer and a second metal stack of the second wafer. A storage device is disposed in a second semiconductor layer of the second wafer. The storage device includes at least N number of storage cells, where each of the N number of storage cells are configured to store a signal representative of image charge accumulated by a respective photodiode region. Each storage cell includes a circuit element that is sensitive to light-induced leakage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.