Multi-chip module architecture
US9478858B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2013 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02A90/10
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Electronically scanned arrays and multi-chip modules (MCMs) that may be used in such arrays are provided. One MCM may include a set of one or more first semiconductor components and a plurality of second semiconductor components. The first semiconductor component set is coupled to the plurality of second semiconductor components, and the first semiconductor component set is configured to control the plurality of second semiconductor components. Each of the plurality of second semiconductor components is accessible through a plurality of data strings providing communication between the first semiconductor component set and the plurality of second semiconductor components, each data string defining a unique path between the first semiconductor component set and the plurality of second semiconductor components, such that the plurality of data strings provide redundant data paths between the first semiconductor component set and the plurality of second semiconductor components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.