Amplifier circuit and operation method thereof
US9479119B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2013 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Nov 8, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0408
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is an amplifier circuit capable of achieving high efficiency at back off power while maintaining high output power when an amplifier of a driving stage is saturated in a multistage amplifier in which a plurality of amplifiers are connected in series to each other. In the amplifier circuit, at least two amplifiers including a first amplifier and a second amplifier, the first amplifier preceding the second the first amplifier, are connected in series to each other, the second amplifier changes input impedance according to output power from the first amplifier, and an impedance adjusting unit for adjusting output load impedance of the first amplifier is disposed between the first amplifier and the second amplifier, wherein the impedance adjusting unit optimizes the output load impedance of the first amplifier according to a change of input impedance of the second amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.