Patent · US Active

Complex-pole load offering concurrent image rejection and channel selection

US9479140B2 · kind B2 · utility

2Cited by

0References

2Claims

0Family size

Assignee

University of Macau · CN

Inventors

Zhicheng Lin · Fujian, CN
Pui-In Mak · Macau, CN
Rui Paulo da Silva Martins · Macau, CN

Key dates

Filing date	Apr 17, 2014
Grant date	Oct 25, 2016
Priority date	—
Expiry date	Apr 17, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH04B2001/1072
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A complex-pole load is configured as a parallel circuit, having 4 transistors arranged in pairs. Each pair of transistors has a transistor gated by a control voltage sources, and connected in parallel with a transistor diode connected for gating by the respective input. The control voltage sources result in the circuit synthesizing a first order complex pole at a positive IF (+IF) or a negative IF (−IF) for channel selection and image rejection, offering image rejection and channel selection concurrently.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.