Methods and circuits for protecting integrated circuits from reverse engineering
US9479176B1 · kind B1 · utility
11Cited by
37References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 25, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Nov 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17768
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A camouflage circuit instantiated on a semiconductor substrate includes a transient-comparison circuit that briefly expresses a value representative of either a one or a zero in dependence upon reference elements that are visibly indistinct from a perspective normal to the planar surface substrate surface, but that nevertheless exhibit distinct electrical responses. Transient comparisons that define logic states only briefly vastly complicate the use of reverse-engineering tools and techniques that rely on optical stimulation to sense when transistors are on or off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.