Self-calibrating fractional divider circuits
US9479177B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Apr 30, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional divider (FD) includes a multi-modulus divider (MMD), which generates a periodic output signal in response to: (i) a periodic reference signal (REFHF), and (ii) a modulus control signal having a value that sets a frequency division ratio (1/P, 1/(P+1)) to be applied to the periodic reference signal. A phase correction circuit is provided, which generates an FD output signal in response to the periodic MMD output signal and a corrected multi-bit phase correction control (CPCC) signal during an active mode of operation. The phase correction circuit further generates an FD output signal in response to the periodic MMD output signal and a preliminary multi-bit phase correction control (PPCC) signal during a calibration mode of operation. A control circuit is provided, which generates the modulus control signal, the PPCC signal and the CPCC signal during the active mode of operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.