Successive approximation register-based analog-to-digital converter with increased time frame for digital-to-analog capacitor settling
US9479190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2014 |
| Grant date | Oct 25, 2016 |
| Priority date | — |
| Expiry date | Jan 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/125
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Embodiments relate to successive approximation register (SAR)-based analog-to-digital converters (ADCs) that increase a time frame allocated for the settling of capacitors in a digital-to-analog converter (DAC) capacitor network by feeding a comparator output signal to the DAC to begin DAC capacitor settling before the comparator output is latched by a clock signal at a latching time. The SAR ADC can include a window circuit that provides the comparator output directly from the comparator to the DAC before the latching time of the comparator. After the latching time, the latched version of the comparator output is provided to the DAC capacitor. By providing the capacitor output to the DAC capacitor before latching, DAC capacitor can settle earlier compared to an SAR ADC where DAC capacitor settling begins after the latching time of the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.