Differential stack-based symmetric co-routines
US9483303B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Feb 29, 2012 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jan 1, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device initiates execution of a first co-routine on the computing device. The first co-routine utilizes an execution stack in a memory of the computing device. A differential symmetric co-routine module pauses execution of the first co-routine and, subsequently, resumes execution of the first co-routine utilizing the same execution stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.