Locking a system management interrupt (SMI) enable register of a chipset
US9483426B2 · kind B2 · utility
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9References
15Claims
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Assignee
Inventors
Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jan 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Example embodiments disclosed herein relate to locking a system management interrupt (SMI) enable register of a chipset. Example embodiments include at least one contact configuration register to configure a contact of a chipset, and a contact SMI enable register of a chipset to store an enable value or a disable value. In example embodiments, the disable value stored in the contact SMI enable register is to prevent the chipset from providing an SMI request to a processor in response to an SMI signal received at the contact. Example embodiments further include locking the contact SMI enable register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.