Patent · US Active

Assuring chip reliability with automatic generation of drivers and assertions

US9483591B1 · kind B1 · utility

1Cited by
4References
20Claims
0Family size

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Key dates

Filing dateNov 27, 2015
Grant dateNov 1, 2016
Priority date
Expiry dateNov 27, 2035

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2119/02
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A computer-implemented method may include retrieving a design netlist with a processor, identifying, via the processor, a logic structure in the design netlist, generating, via the processor, a driver based on the logic structure, applying, via the processor, a simulation and a formal model based on the driver, and testing, via the processor, an output of the simulation and the formal model.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.