Method for decomposing a hardware model and for accelerating formal verification of the hardware model
US9483593B2 · kind B2 · utility
2Cited by
8References
19Claims
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Key dates
| Filing date | Aug 20, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Aug 20, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described is a method performed by a computing device, the method comprises: deriving a hierarchal structure of hardware instances of a hardware block, wherein the hardware block is described in a register transfer language (RTL); determining complexity of at least one hardware instance, in the hierarchal structure, with reference to a complexity metric; identifying, in response to the determined complexity of the at least one hardware instance, whether the at least one hardware instance is to be modeled; and modifying the hierarchal structure with information about the to be modeled hardware instance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.