Multi supply cell arrays for low power designs

US9483600B2 · kind B2 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Mamta Bansal · San Diego, US
• Uday Doddannagari · San Diego, US
• Paras Gupta · San Diego, US
• Ramaprasath Vilangudipitchai · San Diego, US
• Parissa Najdesamii · San Diego, US
• Dorav Kumar · San Diego, US
• Nitin Partani · Nagamangala, IN

Key dates

• Filing date: Mar 11, 2015
• Grant date: Nov 1, 2016
• Expiry date: Mar 23, 2035

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D30/70
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A MOS device includes a number of standard cells configured to reduce routing congestions while providing area savings on the MOS device. The standard cells may be single height standard cells that share an n-type well isolated from other nearby n-type wells. The input and output signal pins of the single height standard cells may be configured in a lowest possible metal layer (e.g., M1), while the secondary power pins of the single height standard cells may be configured in a higher metal layer (e.g., M2). Interconnects supplying power to secondary power pins may be configured along vertical tracks and shared among different sets of standard cells, which may reduce the number of vertical tracks used in the MOS device. The number of available horizontal routing tracks in the MOS device may remain unaffected, since the horizontal tracks already used by the primary power/ground mesh are used for power connection.