Offset contacts for reduced off capacitance in transistor switches
US9484305B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jul 20, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses and methods for reduced OFF capacitance in switching devices are disclosed. A semiconductor die may include a semiconductor substrate, first and second elongated doped regions, said first region serving as a source of a first transistor, said second region serving as a drain of the first transistor and a source of a second transistor. The semiconductor die further includes a plurality of elongated gate structures including a first gate structure disposed between the first and second regions and serving as a gate of the first transistor. The semiconductor die further includes a first set of evenly-spaced electrical contact pads disposed on the first region, and a second set of evenly-spaced electrical contact pads disposed on the second region, the second set of contact pads being offset with respect to the first set of contact pads in a longitudinal direction of the first and second regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.