Chip package and packaging method
US9484311B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Dec 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package and a packaging method are provided, which relates to the field of communications technologies, and is invented to implement high-frequency electromagnetic interference shielding and effectively improve chip performance. The package includes a package substrate and a metal cap covering the package substrate, where a silicon chip placement area is arranged on an upper surface of the package substrate, multiple first conductive parts are arranged in a peripheral area of the silicon chip placement area, and an edge of the metal cap is in contact with the package substrate and electrically connected to the multiple first conductive parts, where at least a portion of first conductive parts in the multiple first conductive parts are electrically connected to a grounding part by using the metal cap, and the grounding part is arranged on the package substrate, and configured to ground the package substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.