Array substrate, manufacturing method thereof and display device
US9484465B2 · kind B2 · utility
2Cited by
1References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 9, 2013 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Dec 9, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F1/134372
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A array substrate is disclosed. The array substrate includes: a substrate (10); and a first gate metal layer (111), a first gate insulating layer (121), a semiconductor layer (13) and a source-drain electrode layer (14) disposed in this order on the substrate from bottom to top. The array substrate (10) further includes a second gate insulating layer (122) disposed on the source-drain electrode layer (14); and a second gate metal layer (112) disposed on the second gate insulating layer (122). A method of manufacturing an array substrate is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.