Dual edge pulse de-multiplexer with equalized path delay
US9484918B1 · kind B1 · utility
2Cited by
41References
15Claims
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Key dates
| Filing date | Aug 25, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Aug 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B7/0671
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A pulse domain 1 to 2N demultiplexer has a (i) pair of N stage counters each of which is responsive to an incoming pulse train in the pulse domain, one of the counters being responsive to leading edges of the pulses in the incoming pulse train and the other one of the counters being responsive to trailing edges of the pulses in the incoming pulse train and (ii) a control logic responsive to the states through which the pair of counters count, the control logic including 2N gate arrangements, each of the 2N gate arrangements generating a output signal of the pulse domain 1 to 2N demultiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.