Techniques for fractional-N phase locked loops

US9484939B2 · kind B2 · utility

Assignee

• Lattice Semiconductor Corporation · US

Inventors

• Kexin Luo · Shanghai, CN
• Kai Zhou · Shanghai, CN
• Shengguo CAO · Shanghai, CN
• Lingfen Yue · Shanghai, CN
• Fangquing Chu · Mountain View, US
• Yu Shen · Taoyuan, TW
• Zhi Wu · Shanghai, CN

Key dates

• Filing date: May 16, 2014
• Grant date: Nov 1, 2016
• Expiry date: Dec 1, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M3/30
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

Embodiments describe techniques for utilizing fractional-N phase locked loops (PLL). Some embodiments describe a fractional-divider based fractional-N PLL for a spread spectrum clock (SSC) generator that utilizes phase average techniques to suppress phase interpolator nonlinearity. Some embodiments describe a fractional-N PLL based on fractional dividers with hybrid finite impulse response (FIR) filtering. Some embodiments describe a small size and low power divider for a hybrid FIR fractional-N PLL.