Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
US9484941B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2016 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jan 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0836
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A negative-capacitance circuit comprises a first node coupled to a drain of a first transistor and a gate of a second transistor; a second node coupled to a drain of the second transistor and a gate of the first transistor; a capacitor coupled between a source of the first transistor and a source of the second transistor; a first current mirror coupled between a supply voltage and the source of the first transistor; and a second current mirror coupled between the supply voltage and the source of the second transistor. The circuit can be configured to drive the differential capacitive load between the first and second nodes in a shorter time period, thereby increasing the transfer bandwidth of the differential signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.