Method for duty cycle distortion detection through decision feedback equalizer taps
US9484967B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | May 11, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/24
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment includes a receiver circuit, a feedback circuit and a control circuit. The receiver circuit is configured to receive each data bit of a plurality of data bits. The feedback circuit is configured to measure a first interference level generated by a first data bit of a first subset of the plurality of data bits on a second data bit of the plurality of data bits to generate one of a first plurality of feedback values. The feedback circuit is also configured to measure a second interference level generated by a third data bit of a second subset of the plurality of data bits on a fourth data bit of the plurality of data bits to generate one of a second plurality of feedback values. The control circuit is configured to determine a duty cycle dependent upon a comparison of the first plurality to the second plurality.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.