Multiphase clock data recovery circuit calibration
US9485080B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Sep 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus, and systems for clock calibration are disclosed. A method for clock data recovery circuit calibration includes configuring a first clock recovery circuit to provide a clock signal that has a first frequency and that includes a single pulse for each symbol transmitted on a 3-wire, 3-phase interface, and calibrating the first clock recovery circuit by incrementally increasing a delay period provided by a delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that is less than the first frequency and, when the first clock recovery circuit has a frequency that is less than the first frequency, incrementally decreasing the delay period provided by the delay element of the first clock recovery circuit until the clock signal provided by the first clock recovery circuit has a frequency that matches the first frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.