Linearity of phase interpolators by combining current coding and size coding
US9485084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 2014 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jun 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00065
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase interpolator, including: a first portion including a first plurality of branches and a plurality of tail current sources, each branch including a differential pair of transistors, source terminals of the differential pair of transistors connect to form a source node, wherein each tail current source couples to one of the source nodes, and wherein the differential pair of transistors and the corresponding tail current source are configured in a current coding scheme; a second portion including a second plurality of branches and a fixed current source coupled to the second plurality of branches, each branch of the second plurality of branches including a second plurality of differential pairs of transistors and a plurality of switches configured in a size coding scheme; wherein the first portion and the second portion are coupled to each other and to a pair of load resistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.