Digital baud rate clock recovery of heavily ISI-induced signals
US9485121B2 · kind B2 · utility
1Cited by
3References
7Claims
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Key dates
| Filing date | Jan 26, 2015 |
| Grant date | Nov 1, 2016 |
| Priority date | — |
| Expiry date | Jan 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03636
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
System and method for digitally equalizing a data channel having wide channel impulse response for clock recovery of heavily ISI-induced received signals operating at one sample per symbol, according to which the received signal is pre-processed to provide a received signal with modified constellation, which is pre-processed for the decision process of signal with Inter-Symbol Interference by introducing controlled ISI to the received signal. The decision process is performed, based on a higher order vocabulary according to the introduced controlled ISI.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.