Mode based skew to reduce scan instantaneous voltage drop and peak currents
US9488692B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 5, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318575
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.