Array substrate, method for fabricating the same and display device
US9488855B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Aug 9, 2013 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Aug 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Provided are an array substrate, a method for fabricating the same and a display device. The array substrate comprises: a transparent pixel electrode, a first data line and a first transparent common electrode, the array substrate further comprises: a second data line and an insulating layer having a via hole disposed in an non-aperture region of the array substrate, the second data line is connected to an extension of the transparent pixel electrode and connected to the second transparent common electrode through the via hole in the insulting layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.