Interrupt driven memory signaling
US9489136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jun 23, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments includes an interrupt-driven data transport architecture utilizing a memory channel bus. For example, a first logic component at a first computing device can initiate a data access request involving a second logic component at a second computing device. The first logic component can store request information associated with the data access request in a predefined memory space of a memory module connected via a memory channel bus to the first logic component and the second logic component. The first logic component can then generate a request-ready interrupt signal through one or more redundant pins of the memory channel bus. The second logic component can be triggered by the interrupt signal to read the request information from the predefined memory space. The second logic component can use that information to complete the request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.