Methods and apparatus for joint scheduling and layout optimization to enable multi-level vectorization
US9489180B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2012 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Nov 16, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/447
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one vector execution unit that allow for parallel execution of tasks on constant-strided memory locations. The first custom computing apparatus optimizes the code for parallelism, locality of operations, constant-strided memory accesses and vectorized execution on the second computing apparatus. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.