Highly efficient different precision complex multiply accumulate to enhance chip rate functionality in DSSS cellular systems
US9489197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 9, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention is a digital signal processor capable of performing correlation of data with pseudo noise for code division multiple access (CDMA) decoding using clusters. Each cluster includes plural multipliers. The multipliers multiply real and imaginary parts of packed data by corresponding pseudo noise data. Within a cluster the real parts and the imaginary parts of the products are summed separately. This forms plural complex number outputs equal in number to the number of clusters. The pseudo noise data is offset relative to the data input differing amounts for different clusters. The clusters are divided into first half clusters receiving data from even numbered slots and second half clusters receiving data from odd numbered slots. The correlation unit includes a mask input to selectively zero a multiplier product.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.