Method and apparatus for asynchronous processor with fast and slow mode
US9489200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | May 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/3883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock-less asynchronous processing circuit or system is configured to operation in a plurality of modes. In an initialization mode (e.g., reset, initialization, boot up), a self-clocked generator associated with the asynchronous circuit is configured to generate an active complete signal (to latch output processed data) within a first period of time after receiving a trigger signal. In a normal mode, the self-clocked generator is configured to generate the active complete signal within a second period of time after receiving the trigger signal. In one embodiment, during the initialization mode, the asynchronous circuit latches the output slower than when in the normal mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.