Processor and method for partially flushing a dispatched instruction group including a mispredicted branch
US9489207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2009 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Mechanisms are provided for partial flush handling with multiple branches per instruction group. The instruction fetch unit sorts instructions into groups. A group may include a floating branch instruction and a boundary branch instruction. For each group of instructions, the instruction sequencing unit creates an entry in a global completion table (GCT), which may also be referred to herein as a group completion table. The instruction sequencing unit uses the GCT to manage completion of instructions within each outstanding group. Because each group may include up to two branches, the instruction sequencing unit may dispatch instructions beyond the first branch, i.e. the floating branch. Therefore, if the floating branch results in a misprediction, the processor performs a partial flush of that group, as well as a flush of every group younger than that group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.