Patent · US Active

System and method for managing bandwidth and power consumption through data filtering

US9489305B2 · kind B2 · utility

2Cited by

4References

27Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

George Patsilaras · San Diego, US
Bohuslav Rychlik · San Diego, US
Andrew E. Turner · San Diego, US
Kris Tiri · San Diego, US
Jeong-Ho Woo · San Diego, US
Anwar Rohillah · San Diego, US
Feng Wang · Sunnyvale, US
Moinul Khan · San Jose, US
Subbarao Palacharla · San Diego, US

Key dates

Filing date	Dec 16, 2014
Grant date	Nov 8, 2016
Priority date	—
Expiry date	Jan 31, 2035

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various embodiments of methods and systems for managing write transaction volume from a master component to a long term memory component in a system on a chip (“SoC”) are disclosed. Because power consumption and bus bandwidth are unnecessarily consumed when ephemeral data is written back to long term memory (such as a double data rate “DDR” memory) from a closely coupled memory component (such as a low level cache “LLC” memory) of a data generating master component, embodiments of the solutions seek to identify write transactions that contain ephemeral data and prevent the ephemeral data from being written to DDR.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.