Patent · US Active

Systolic array based architecture for branch and bound algorithms

US9489338B1 · kind B1 · utility

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1References
22Claims
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Assignee

Inventor

  • Yi Ni · Heidelberg, DE

Key dates

Filing dateJan 24, 2014
Grant dateNov 8, 2016
Priority date—
Expiry dateFeb 9, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH04L67/2885
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Techniques and mechanisms implement a branch and bound algorithm using a systolic array based circuit architecture. For example, a systolic array may perform calculations associated with nodes of a tree data structure. Information associated with the nodes may be analyzed and stored by a controller. The controller may also provide data to the systolic array based on the information associated with the nodes.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.