Semiconductor device
US9490208B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 1, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | May 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/391
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a semiconductor chip, a dielectric substrate, and bonding wires. The dielectric substrate includes wiring patterns formed on a surface and a ground metal layer formed on a back side. The semiconductor chip includes an active element and a drain pad that is connected to an output end of the active element. Wiring pattern is formed at a position closer to the drain pad than wiring pattern, wiring pattern and the ground metal layer constitute a first capacitative element, and wiring pattern and the ground metal layer constitute a second capacitative element. The drain pad is connected to wiring pattern through bonding wire, and connected to wiring pattern through bonding wire. Bonding wire and the first capacitative element constitute a high-pass matching circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.