Semiconductor package including a plurality of chips
US9490237B2 · kind B2 · utility
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13References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 9, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jan 9, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A reconfigured wafer of resin-encapsulated semiconductor packages is obtained by supporting with a resin, thereafter, a grinding process is performed on top and backside surfaces to expose only a bump interconnection electrode on a surface of a semiconductor chip. Further, a chip-scale package is obtained by a dicing process along a periphery of the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.