Method for manufacturing thin film transistor array panel
US9490275B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jun 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6755
Abstract
A thin film transistor array panel includes: a gate line on a substrate and including a gate electrode; a first gate insulating layer on the substrate and the gate line, the first gate insulting layer including a first portion adjacent to the gate line and a second portion overlapping the gate line and having a smaller thickness than that of the first portion; a second gate insulating layer on the first gate insulating layer; a semiconductor layer on the second gate insulating layer; a source electrode and a drain electrode spaced apart from each other on the semiconductor layer; a passivation layer on the second gate insulating layer, the source electrode and the drain electrode; and a pixel electrode on the passivation layer and connected with the drain electrode. The first gate insulating layer and the second gate insulating layer have stress in opposite directions from each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.