Manufacturing method and structure of thin film transistor backplane
US9490310B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Mar 8, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/80516
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a manufacture method of a thin film transistor backplane, comprising steps of: providing a substrate (20) with a gate (21), an insulation layer (22) and a semiconducting layer (23); sequentially forming a second metal layer, a reflecting electrode layer and a conductive oxide layer on the substrate (20); implementing one photolithographic process to the second metal layer, the reflecting electrode layer and the conductive oxide layer to pattern the second metal layer, the reflecting electrode layer and the conductive oxide layer for respectively forming a source/a drain (253), a reflecting electrode (252) and a pixel electrode (251), and the source/the drain (253) are connected to the semiconducting layer (23; forming a protective layer on the source/the drain (253), the reflecting electrode (252) and the pixel electrode (251; forming a flat and pixel defining layer (27) on the protective layer (26); forming a photospacer (28) on the flat and pixel defining layer (27).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.