Power semiconductor device and method of fabricating the same and cutoff ring
US9490315B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 12, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jan 12, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5446
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention provides a power semiconductor device and a method of fabricating the same and a cutoff ring. A cutoff ring located at a periphery of an active area of the power semiconductor device is etched forming at least one trench below which an implant area is formed by implanting ions into the trench, and a silicon dioxide dielectric layer covering the trench and a surface of the active area, are formed. Since the ions are implanted into the trench formed by etching the cutoff ring to thereby increase a depth of the implanted ions and a density of the cutoff ring, a width of the cutoff ring can be shortened to thereby address the technical problem of a considerable area of a chip occupied by the cutoff ring and improve a utilization ratio of the area of the chip so as to lower a cost of fabricating the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.