Nonvolatile memory devices and methods of fabricating the same
US9490371B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 12, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Dec 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/69
Abstract
A nonvolatile memory device includes a gate structure including inter-gate insulating patterns that are vertically stacked on a substrate and gate electrodes interposed between the inter-gate insulating patterns, a vertical active pillar connected to the substrate through the gate structure, a charge-storing layer between the vertical active pillar and the gate electrode, a tunnel insulating layer between the charge-storing layer and the vertical active pillar, and a blocking insulating layer between the charge-storing layer and the gate electrode. The charge-storing layer include first and second charge-storing layers that are adjacent to the blocking insulating layer and the tunnel insulating layer, respectively. The first charge-storing layer includes a silicon nitride layer, and the second charge-storing layer includes a silicon oxynitride layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.