Nonvolatile memory device and method for manufacturing same
US9490429B2 · kind B2 · utility
6Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Sep 21, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.