Implementing enhanced bias configuration for CMOS inverter based optical transimpedance amplifier
US9490757B2 · kind B2 · utility
3Cited by
14References
11Claims
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Key dates
| Filing date | Feb 2, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Feb 2, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45264
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and circuit are provided for implementing an enhanced bias configuration for CMOS inverter based optical Transimpedance Amplifiers (TIAs). An operational amplifier is provided in a feedback configuration that forces an input of the CMOS inverter to a set voltage level by regulation of the inverter power supply. A photo-detector sees a more stable bias voltage, and the responsivity of the photo-detector is more robust and the TIA has improved performance across process corners.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.