Neutralization of parasitic capacitance using MOS device
US9490759B2 · kind B2 · utility
1Cited by
5References
23Claims
0Family size
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Key dates
| Filing date | May 27, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Sep 9, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45562
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus comprises an amplifier comprising at least one metal oxide semiconductor (MOS) transistor having a parasitic gate-to-drain capacitance, and at least one MOS neutralization device having a neutralization capacitance configured to compensate for the parasitic gate-to-drain capacitance of the at least one MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.