Cancellation of delta-sigma quantization noise within a fractional-N PLL with a nonlinear time-to-digital converter
US9490818B2 · kind B2 · utility
18Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Jul 31, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M7/3004
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.