Time-to-digital converter using stochastic phase interpolation
US9490831B2 · kind B2 · utility
8Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2015 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Aug 4, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided is a time-to-digital converter. The time-to-digital converter includes several delay circuits, an adder configured to count outputs of the delay circuits, and a least significant bit (LSB) truncation circuit configured to truncate a predetermined number of LSBs from a result output by the adder. The time-to-digital converter is configured to determine a time interval between a start signal and a stop signal within one cycle of a clock having a predetermined period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.