CDR voter with improved frequency offset tolerance
US9490968B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 2014 |
| Grant date | Nov 8, 2016 |
| Priority date | — |
| Expiry date | Aug 11, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An improved clock data recovery circuit is provided which provides lower bit error rates and faster locking times. In an embodiment, the circuit includes a voter having one or more voter inputs. The voter may generate up votes indicative of a recovered clock having a negative phase offset relative to a given voter input, or down votes indicative of the recovered clock having a positive phase offset. The circuit may include a comparator configured to output a phase adjustment signal and a tie signal. The circuit may further include an M-depth shift register and a multiplexer configured to select either the phase adjustment signal or an output from the shift register as a multiplexer output. The circuit may further include a flip-flop that generates a phase adjustment output signal. The shift register may receive the phase adjustment output signal at a data input of the shift register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.