System and method for reducing information leakage from memory
US9495111B2 · kind B2 · utility
6Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2014 |
| Grant date | Nov 15, 2016 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method includes a processing unit connected with a memory, the processing unit configured to access data from the memory. A memory transaction unit is added between the processing unit and the memory. The memory transaction unit is configured to perform dummy read- and write-operations at random memory locations at random times and/or insert random delays before real accesses by the processing unit from the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.